For arithmetic processing devices such as processors, a method of computing a logarithmic function by decomposing the logarithmic function into multiple vice functions and referencing reference tables corresponding to the vice functions at stages of a pipeline has been proposed (refer to, for example, Japanese National Publication of International Patent Application No. 2008-502036). In addition, for arithmetic processing devices, a method of computing an exponential by calculating a coefficient using a table in a case where the exponential is decomposed into a Taylor series operation term and a coefficient term for the Taylor series operation term and computed has been proposed (refer to, for example, International Publication Pamphlet No. WO2013/145276).
For example, a logarithmic function may be decomposed into a Taylor series operation term and a coefficient term for the Taylor series operation term and thereby computed using a Taylor series operation, while the Taylor series operation term is expressed by a Taylor series operation and converses to a value expressed by a finite degree with predetermined precision. Thus, if the Taylor series operation term is truncated to a certain finite degree, predetermined precision is obtained. However, traditionally, since a process of calculating a coefficient is executed in accordance with a combination of multiple instructions such as an instruction to transfer data, an instruction to compute bits, and a shift operation instruction, the computation of the logarithmic function that is executed using the Taylor series operation reduces the processing performance of the arithmetic processing devices.
According to an aspect, an arithmetic processing device and a method of controlling the arithmetic processing device aim to compute a logarithmic function using a series operation at a higher speed than conventional techniques.